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IEICE Trans

Alberto PALACIOS-PAWLOVSKY

A New Algorithm for the Configuration of Fast Adder Trees
Alberto PALACIOS-PAWLOVSKY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2426-2430
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
multiplier, adder, Wallace tree, partial product addition, Dadda tree, 
 Summary | Full Text:PDF