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IEICE Trans

Akira SATOH

A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
Masataka MINAMI Nagatoshi OHKI Hiroshi ISHIDA Toshiaki YAMANAKA Akihiro SHIMIZU Koichiro ISHIBASHI Akira SATOH Tokuo KURE Takashi NISHIDA Takahiro NAGANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 590-596
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAM, full CMOS cell, local interconnect, TiN, 
 Summary | Full Text:PDF