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IEICE Trans

Akira KITAJIMA

Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
Shinsuke KOBAYASHI Yoshinori TAKEUCHI Akira KITAJIMA Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3  pp. 748-754
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
multi-threading, very long instruction word (VLIW), instruction level parallelism, thread level parallelism, HW/SW co-design, 
 Summary | Full Text:PDF
Deriving Concurrent Synchronous EFSMs from Protocol Specifications in LOTOS
Akira KITAJIMA Keiichi YASUMOTO Teruo HIGASHINO Kenichi TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3  pp. 487-494
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
LOTOS, synchronous EFSMs, transformation, multi-rendezvous, implementation, 
 Summary | Full Text:PDF
A Method to Convert Concurrent EFSMs with Multi-Rendezvous into Synchronous Sequential Circuit
Akira KITAJIMA Keiichi YASUMOTO Teruo HIGASHINO Kenichi TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4  pp. 566-575
Type of Manuscript:  Special Section PAPER (Special Section on Concurrent Systems Technology)
Category: 
Keyword: 
communication protocols, multi-rendezvous, concurrent EFSMs, controller synthesis, synchronous sequential circuits, 
 Summary | Full Text:PDF