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IEICE Trans

Abdel MARTINEZ ALONSO

A 7GS/s Complete-DDFS-Solution in 65nm CMOS
Abdel MARTINEZ ALONSO Masaya MIYAHARA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2018/04/01
Vol. E101-C  No. 4  pp. 206-217
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
complete-DDFS-solution, high-speed DDFS, CMOS, RDAC, RSTC-DEM, rail-to-rail operation, two-times interleaved, 
 Summary | Full Text:PDF
A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture
Abdel MARTINEZ ALONSO Masaya MIYAHARA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/10/01
Vol. E99-C  No. 10  pp. 1200-1210
Type of Manuscript:  Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology)
Category: 
Keyword: 
Direct Digital Frequency Synthesizer, Complementary Dual-Phase Latch-Based sequencing method, data sampling rate, CMOS, 
 Summary | Full Text:PDF