Keyword : data sampling rate


A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture
Abdel MARTINEZ ALONSO Masaya MIYAHARA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/10/01
Vol. E99-C  No. 10 ; pp. 1200-1210
Type of Manuscript:  Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology)
Category: 
Keyword: 
Direct Digital Frequency SynthesizerComplementary Dual-Phase Latch-Based sequencing methoddata sampling rateCMOS
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