|
Vol.E71-E No.12
pp.1176-1176
FOREWORD
FOREWORD
Isao SHIRAKAWA, Hiroki KUNIEDA, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1177-1188
REVIEW PAPER
Present and Future Trends in Integrated Analog Signal Processing Circuits
Kenji NAKAYAMA, Atsushi IWATA, Takeshi YANAGISAWA, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1189-1194
REVIEW PAPER
Relaxation-Based Circuit Simulation
Kiichi URAHAMA, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1195-1202
Special SectionPAPER
Parallel Digital Signal Processing with a Multicomputer Type DSP System NOVI
Tetsurou FUJII, Naohisa OHTA, Yukiharu KANAYAMA, Sadayasu ONO, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1203-1211
Special SectionPAPER
A Study on Verification of Service Specification in Communication Software Development
Kenji SHIBATA, Yoshihiro UEDA, Satsuki YUYAMA, Haruo HASEGAWA, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1212-1220
Special SectionPAPER
Reliable and Efficient Fixed Rountings on Digraphs
Yoshifumi MANABE, Makoto IMASE, Terunao SONEOKA, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1221-1228
Special SectionPAPER
Fractal Matrix Model and Its Application to Texture Analysis
Hiroshi KANEKO, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1229-1235
Special SectionPAPER
A Scheme for Mixed-Mode Fault Simulation
Akira MOTOHARA, Motohide MURAKAMI, Miki URANO, Yasuo MASUDA, Masahide SUGANO, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1236-1242
Special SectionPAPER
A Floorplanning Scheme of VLSI Design
Takashi KAMBE, Tuneo TOMITA, |
|
Summary | Full Text:PDF | |
|
Vol.E71-E No.12
pp.1243-1252
Special SectionPAPER
Analog Layout Compaction with a Clean-up Function
Masahiro KAWAKITA, Takahiro WATANABE, |
|
Summary | Full Text:PDF | |
|
Current List: 42521 - 42530
|