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Vol.E75-C No.4
pp.461-466
Special SectionPAPER
An Enhanced Fully Differential Folded-Cascode Op Amp
Katsufumi NAKAMURA, L. Richard CARLEY, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.467-471
Special SectionPAPER
A Dual-Mode Sensing Scheme of Capacitor-Coupled EEPROM Cell
Masanori HAYASHIKOSHI, Hideto HIDAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.472-480
Special SectionPAPER
A 512-kb Flash EEPROM Embedded in a 32-b Microcontroller
Clinton KUO, Mark WEIDNER, Thomas TOMS, Henry CHOE, Ko-Min CHANG, Ann HARWOOD, Joseph JELEMENSKY, Philip SMITH, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.481-486
Special SectionPAPER
A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories
Yoshikazu MIYAWAKI, Takeshi NAKAYAMA, Shin-ichi KOBAYASHI, Natsuo AJIKA, Makoto OHI, Yasushi TERADA, Hideaki ARIMA, Tsutomu YOSHIHARA, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.487-494
Special SectionPAPER
Deep-Submicrometer BiCMOS Circuit Technology for Sub-10-ns ECL 4-Mb DRAM's
Takayuki KAWAHARA, Yoshiki KAWAJIRI, Goro KITSUKAWA, Kazuhiko SAGARA, Yoshifumi KAWAMOTO, Takesada AKIBA, Shisei KATO, Yasushi KAWASE, Kiyoo ITOH, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.495-500
Special SectionPAPER
Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM's
Mikio ASAKURA, Kazutami ARIMOTO, Hideto HIDAKA, Kazuyasu FUJISHIMA, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.501-507
Special SectionPAPER
Word-Line Architecture for Highly Reliable 64-Mb DRAM
Daisaburo TAKASHIMA, Yukihito OOWAKI, Ryu OGIWARA, Yohji WATANABE, Kenji TSUCHIDA, Masako OHTA, Hiroaki NAKANO, Shigeyoshi WATANABE, Kazunori OHUCHI, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.508-515
Special SectionPAPER
A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's
Hideto HIDAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.516-523
Special SectionPAPER
A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier
Travis N. BLALOCK, Richard C. JAEGER, |
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Summary | Full Text:PDF | |
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Vol.E75-C No.4
pp.524-529
Special SectionPAPER
Temperature-Compensation Circuit Techniques for High-Density CMOS DRAM's
Dong-Sun MIN, Sooin CHO, Dong Soo JUN, Dong-Jae LEE, Yongsik SEOK, Daeje CHIN, |
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Summary | Full Text:PDF | |
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