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Vol.E77-C No.8
pp.1249-1250
FOREWORD
FOREWORD
Fujio MASUOKA, |
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Summary | Full Text:PDF | |
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Vol.E77-C No.8
pp.1251-1259
INVITED PAPER
Non-volatile Memory
Sub-Halfmicron Flash Memory Technologies
Koji SAKUI, Fujio MASUOKA, |
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Summary | Full Text:PDF | |
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Vol.E77-C No.8
pp.1260-1269
Special SectionPAPER
Non-volatile Memory
A 3 Volt 1 Mbit Full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology
Shin-ichi MINAMI, Kazuaki UJIIE, Masaaki TERASAWA, Kazuhiro KOMORI, Kazunori FURUSAWA, Yoshiaki KAMIGAKI, |
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Summary | Full Text:PDF | |
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Vol.E77-C No.8
pp.1270-1278
Special SectionPAPER
Non-volatile Memory
Highly Reliable Flash Memories Fabricated by in-situ Multiple Rapid Thermal Processing
Takahisa HAYASHI, Yoshiyuki KAWAZU, Akira UCHIYAMA, Hisashi FUKUDA, |
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Summary | Full Text:PDF | |
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Vol.E77-C No.8
pp.1279-1286
Special SectionPAPER
Non-volatile Memory
Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories
Hiroshi ONODA, Yuichi KUNORI, Kojiro YUZURIHA, Shin-ichi KOBAYASHI, Kiyohiko SAKAKIBARA, Makoto OHI, Atsushi FUKUMOTO, Natsuo AJIKA, Masahiro HATANAKA, Hirokazu MIYOSHI, |
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Summary | Full Text:PDF | |
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Vol.E77-C No.8
pp.1287-1295
Special SectionPAPER
Non-volatile Memory
Data Retention Characteristics of Flash Memory Cells after Write and Erase Cycling
Seiichi ARITOME, Riichiro SHIROTA, Koji SAKUI, Fujio MASUOKA, |
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Summary | Full Text:PDF | |
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Vol.E77-C No.8
pp.1296-1302
Special SectionPAPER
Non-volatile Memory
A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories
Kohji KANAMORI, Yosiaki S. HISAMUNE, Taishi KUBOTA, Yoshiyuki SUZUKI, Masaru TSUKIJI, Eiji HASEGAWA, Akihiko ISHITANI, Takeshi OKAZAWA, |
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Vol.E77-C No.8
pp.1303-1315
INVITED PAPER
DRAM
High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA, Tohru FURUYAMA, |
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Vol.E77-C No.8
pp.1316-1322
Special SectionPAPER
DRAM
PATDRAM: Pixel-Aligned Triple-Port DRAM
Toshiki MORI, Tetsuyuki FUKUSHIMA, Akifumi KAWAHARA, Katsumi WADA, Akihiro MATSUMOTO, |
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Vol.E77-C No.8
pp.1323-1327
Special SectionPAPER
DRAM
A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs
Tadahiko SUGIBAYASHI, Isao NARITAKE, Hiroshi TAKADA, Ken INOUE, Ichiro YAMAMOTO, Tatsuya MATANO, Mamoru FUJITA, Yoshiharu AIMOTO, Toshio TAKESHIMA, Satoshi UTSUGI, |
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Summary | Full Text:PDF | |
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