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Vol.E80-D No.10
pp.1009-1016
Special SectionPAPER
Logic Design
Generating Random Benchmark Circuits with Restricted Fan-Ins
Kazuo IWAMA, Kensuke HINO, Hiroyuki KUROKAWA, Sunao SAWADA, |
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Vol.E80-D No.10
pp.1017-1023
Special SectionPAPER
Logic Design
Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution
Hiroshi SAWADA, Takayuki SUYAMA, Akira NAGOYA, |
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Summary | Full Text:PDF | |
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Vol.E80-D No.10
pp.1024-1031
Special SectionPAPER
Physical Design
Estimating Interconnection Lengths in Three-Dimensional Computer Systems
Dirk STROOBANDT, Jan VAN CAMPENHOUT, |
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Summary | Full Text:PDF | |
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Vol.E80-D No.10
pp.1032-1043
Special SectionPAPER
Physical Design
Non-deterministic Constraint Generation for Analog and Mixed-Signal Layout
Edoardo CHARBON, Enrico MALAVASI, Paolo MILIOZZI, Alberto SANGIOVANNI-VINCENTELLI, |
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Vol.E80-A No.9
pp.1539-1539
FOREWORD
FOREWORD
Akio USHIDA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.9
pp.1540-1547
Special SectionPAPER
On the Stability of Operating Points of Transistor Circuits
Tetsuo NISHI, Masato OGATA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.9
pp.1548-1533
Special SectionPAPER
Emergent Synchronization in Multi-Elevator System and Dispatching Control
Takashi HIKIHARA, Shinichi UESHIMA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.9
pp.1554-1559
Special SectionPAPER
Automatic Adjustment of Delay Time and Feedback Gain in Delayed Feedback Control of Chaos
Hiroyuki NAKAJIMA, Hideo ITO, Yoshisuke UEDA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.9
pp.1560-1566
Special SectionPAPER
A Method to Calculate Homoclinic Points of a Two-Dimensional Noninvertible Map
Tetsuya YOSHINAGA, Hiroyuki KITAJIMA, Hiroshi KAWAKAMI, Christian MIRA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.9
pp.1567-1571
Special SectionPAPER
Bifurcation from a Chaos Generator Including Switched Inductor with Time Delay
Masanobu KUBOSHIMA, Toshimichi SAITO, |
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Summary | Full Text:PDF | |
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Current List: 36181 - 36190
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