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Vol.E82-A No.1
pp.145-158 PAPER
VLSI Design Technology and CAD The Integrated Scheduling and Allocation of High-Level Test Synthesis Tianruo YANG, |
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Vol.E82-A No.1
pp.159-166 PAPER
VLSI Design Technology and CAD A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits Masanori HASHIMOTO, Hidetoshi ONODERA, Keikichi TAMARU, |
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Vol.E82-A No.1
pp.167-172 PAPER
Numerical Analysis and Optimization An Algorithm for Finding All Solutions of a Hysteresis Neural Network Yuji KOBAYASHI, Kenya JIN'NO, Toshimichi SAITO, |
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Vol.E82-A No.1
pp.173-177 LETTER
Numerical Analysis and Optimization Floating-Point Divide Operation without Special Hardware Supports Takashi AMISAKI, Umpei NAGASHIMA, Kazutoshi TANABE, |
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Vol.E82-B No.1
pp.1-13 PAPER
Communication Networks and Services PPCN: A High-Performance Copy Network for Large Scale ATM Switching Systems Wen-Tsuen CHEN, Yao-Wen DENG, |
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Vol.E82-B No.1
pp.14-23 PAPER
Communication Networks and Services Call Admission Control for QoS Provisioning in Multimedia Wireless ATM Networks Doo Seop EOM, Masashi SUGANO, Masayuki MURATA, Hideo MIYAHARA, |
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Vol.E82-B No.1
pp.24-33 PAPER
Communication Networks and Services Subjective Assessment of Stored Media Synchronization Quality in the VTR Algorithm Fadiga KALADJI, Yutaka ISHIBASHI, Shuji TASAKA, |
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Vol.E82-B No.1
pp.34-38 PAPER
Switching and Communication Processing On Priority Scheduling Algorithm at ATM Switches with Multi-Class Output Buffers Kwang-Hyun SHIM, Ji-Myong NHO, Jong-Tae LIM, |
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Vol.E82-B No.1
pp.39-47 PAPER
Switching and Communication Processing Fast Admission Control for Rate Monotonic Schedulers Tsern-Huei LEE, An-Bang CHANG, |
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Vol.E82-B No.1
pp.48-59 PAPER
Switching and Communication Processing A Refined Model for Performance Analysis of Buffered Banyan Networks with and without Priority Control King-Sun CHAN, Kwan L. YEUNG, Sammy C. H. CHAN, |
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Current List: 34721 - 34730
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