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Vol.E82-C No.9
pp.1599-1606
Special SectionPAPER
Quantum Devices and Circuits
A Compact Model for the Current-Voltage Characteristics of a Single Electron Transistor in the Resonant Transport Mode
Kenji NATORI, Nobuyuki SANO, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1607-1614
Special SectionPAPER
Quantum Devices and Circuits
Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit
Masamichi AKAZAWA, Kentarou KANAAMI, Takashi YAMADA, Yoshihito AMEMIYA, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1615-1622
Special SectionPAPER
Quantum Devices and Circuits
A Multiple-Valued Hopfield Network Device Using Single-Electron Circuits
Takashi YAMADA, Yoshihito AMEMIYA, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1623-1629
Special SectionPAPER
Quantum Devices and Circuits
Analog Computation Using Coupled-Quantum-Dot Spin Glass
Nan-Jian WU, Hassu LEE, Yoshihito AMEMIYA, Hitoshi YASUNAGA, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1630-1637
Special SectionPAPER
Application of Resonant Tunneling Devices
Design and Analysis of Resonant-Tunneling-Diode (RTD) Based High Performance Memory System
Tetsuya UEMURA, Pinaki MAZUMDER, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1638-1646
Special SectionPAPER
Application of Resonant Tunneling Devices
Ultra-Fast Optoelectronic Decision Circuit Using Resonant Tunneling Diodes and a Uni-Traveling-Carrier Photodiode
Kimikazu SANO, Koichi MURATA, Taiichi OTSUJI, Tomoyuki AKEYOSHI, Naofumi SHIMIZU, Masafumi YAMAMOTO, Tadao ISHIBASHI, Eiichi SANO, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1647-1654
Special SectionPAPER
Non-Binary Architectures
Compact Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits
Shugang WEI, Kensuke SHIMIZU, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1655-1661
Special SectionPAPER
Non-Binary Architectures
New Non-Volatile Analog Memory Circuits Using PWM Methods
Shigeo KINOSHITA, Takashi MORIE, Makoto NAGATA, Atsushi IWATA, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1662-1668
Special SectionPAPER
Non-Binary Architectures
Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic
Takahiro HANYU, Michitaka KAMEYAMA, |
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Summary | Full Text:PDF | |
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Vol.E82-C No.9
pp.1669-1677
Special SectionPAPER
Non-Binary Architectures
A Code-Division Multiplexing Technique for Efficient Data Transmission in VLSI Systems
Yasushi YUMINAKA, Kazuhiko ITOH, Yoshisato SASAKI, Takafumi AOKI, Tatsuo HIGUCHI, |
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Summary | Full Text:PDF | |
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Current List: 34071 - 34080
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