Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D
No. 10 ;
pp. 1605-1608
Type of Manuscript:
Special Section LETTER (Special Issue on Test and Verification of VLSI)
Category: Keyword: synthesis for testability, redundancy removal, sequential circuit, undetectable faults, unreachable states, |