Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/10/25 Vol. E80-DNo. 10 ;
pp. 1001-1008 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Design Keyword: three-level networks, AND-EXOR, logic minimization, complexity of logic networks, NP-equivalence,