Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2017/07/01 Vol. E100-ANo. 7 ;
pp. 1488-1495 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: weighted fault coverage, critical area, test cost reduction, test pattern reduction, bridge fault, open fault,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-DNo. 10 ;
pp. 1498-1505 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: BIST Keyword: at-speed test, BISR, embedded DRAM, test cost reduction,