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Statechart Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems
Rakefet KOL Ran GINOSAR Goel SAMUEL | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/03/25
Vol. E80-D
No. 3 ;
pp. 308-314
Type of Manuscript:
Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
Category: Specification Description
Keyword:
asynchronous logic design, statechart, validation, synthesis, | | | Summary | Full Text:PDF | |
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