Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D
No. 10 ;
pp. 1571-1578
Type of Manuscript:
Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Debugging Multiple Processors
Keyword:
VLSI, debug methodology, heterogeneous multiple processor, IEEE 1149.1, reducing debug period, |