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IEICE Trans

Keyword : processor array with separable buses

Algorithms for Matrix Multiplication and the FFT on a Processor Array with Separable Buses
Takashi MAEBA Mitsuyoshi SUGAYA Shoji TATSUMI Ken'ichi ABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/01/01
Vol. E86-D  No. 1 ; pp. 136-140
Type of Manuscript:  LETTER
Category: Algorithms
Keyword: 
processor array with separable buses, matrix multiplication, fast Fourier transform, parallel algorithm, area-time complexity, 
 Summary | Full Text:PDF