Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D
No. 3 ;
pp. 620-629
Type of Manuscript:
Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing Keyword: test scheduling, test access mechanism design, preemptive scheduling, system-on-chip testing, |