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IEICE Trans

Keyword : parallel weight counter

A Design Method for Cost-Effective Self-Testing Checker for Optimal d-Unidirectional Error Detecting Codes
Eiji FUJIWARA Masakatsu YOSHIKAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6 ; pp. 771-777
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
self-testing checker, d-UED codes, new residue operation, parallel weight counter, modulo adder, 
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