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IEICE Trans

Keyword : parallel programming language

Performance Evaluation of Neural Network Hardware Using Time-Shared Bus and Integer Representation Architecture
Moritoshi YASUNAGA Tatsuo OCHIAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/06/25
Vol. E79-D  No. 6 ; pp. 888-896
Type of Manuscript:  PAPER
Category: Bio-Cybernetics and Neurocomputing
Keyword: 
neural networks, parallel computing, parallel programming language, performance evaluation, scalability, 
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