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IEICE Trans

Keyword : memory-level parallelism

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control
Hideki ANDO Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/02/01
Vol. E99-D  No. 2 ; pp. 341-350
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessor, superscalar processor, memory-level parallelism, instruction-level parallelism, power consumption, 
 Summary | Full Text:PDF
MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism
Yuya KORA Kyohei YAMAGUCHI Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12 ; pp. 3110-3123
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessor, superscalar processor, memory-level parallelism, instruction-level parallelism, 
 Summary | Full Text:PDF