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IEICE Trans

Keyword : logic design verification

Implicit Representation and Manipulation of Binary Decision Diagrams
Hitoshi YAMAUCHI Nagisa ISHIURA Hiromitsu TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 354-362
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
binary decision diagram (BDD), representation of Boolean functions, logic design verification, logic synthesis, implicit representation of graphs, 
 Summary | Full Text:PDF
Towards Verification of Bit-Slice Circuits--Time-Space Modal Model Checking Approach--
Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 791-795
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
formal verification, time-space modal logic, symbolic model checking, logic design verification, verification of bit-slice circuits, 
 Summary | Full Text:PDF