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IEICE Trans

Keyword : instruction level parallel processor

A Concurrent Fault Detection Method for Instruction Level Parallel Processors
Alberto PALACIOS PAWLOVSKY Makoto HANAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 755-762
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
instruction level parallel processor, fault-tolerance, concurrent fault detection, NOP slots, stalled cycles, 
 Summary | Full Text:PDF