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IEICE Trans

Keyword : gate-level fault

SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 826-831
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fault diagnosis, gate-level fault, combinational circuit, probing, 
 Summary | Full Text:PDF