An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System Kazuo KAWAKUBOHiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/25 Vol. E76-DNo. 7 ;
pp. 763-770 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: fail-safe, fault tolerance, formal verification, temporal logic,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-DNo. 5 ;
pp. 577-585 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Fail-Safe/Fault Tolerant Keyword: fault tolerance, multiple-valued logic, fail-safe, threshold operation, power press control,