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IEICE Trans

Keyword : defect level

Effect of BIST Pretest on IC Defect Level
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/10/01
Vol. E89-D  No. 10 ; pp. 2626-2636
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BIST, fault coverage, defect level, 
 Summary | Full Text:PDF
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6 ; pp. 1210-1216
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BIST, fault coverage, defect level, 
 Summary | Full Text:PDF
Defect Level Prediction Using Multi-Model Fault Coverage
Shyue-Kung LU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/06/01
Vol. E87-D  No. 6 ; pp. 1488-1495
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
defect level, fault coverage, multi-model fault coverage, yield, 
 Summary | Full Text:PDF
The Effect of CMOS VLSI IDDq Measurement on Defect Level
Junichi HIRASE Masanori HAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 839-844
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
IDDq test, CMOS VLSI, fault coverage, defect level, toggle rate, stuck-at fault, design for testability, 
 Summary | Full Text:PDF