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IEICE Trans

Keyword : core testing

Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/05/01
Vol. E88-D  No. 5 ; pp. 984-992
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
hybrid pattern BIST, core testing, test cost reduction, FPGA core, reconfigurable system-on-a-chip, 
 Summary | Full Text:PDF