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IEICE Trans

Keyword : coherence protocol

A Selective Invalidation Strategy for Cache Coherence
Cosimo Antonio PRETE Gianpaolo PRINA Luigi RICCIARDI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/10/25
Vol. E78-D  No. 10 ; pp. 1316-1320
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
cache, coherence protocol, multiprocessor, 
 Summary | Full Text:PDF