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IEICE Trans

Keyword : co-design verification

Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions
Kiyoharu HAMAGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 637-641
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSI)
Category: 
Keyword: 
formal verification, high-level design verification, uninterpreted function, co-design verification, 
 Summary | Full Text:PDF
Verifying Signal-Transition Consistency of High-Level Designs Based on Symbolic Simulation
Kiyoharu HAMAGUCHI Hidekazu URUSHIHARA Toshinobu KASHIWABARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1587-1594
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Verification
Keyword: 
formal verification, high-level design verification, uninterpreted function, co-design verification, 
 Summary | Full Text:PDF