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IEICE Trans

Keyword : clock line

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6 ; pp. 1323-1331
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generation, fault simulation, clock line, delay fault, 
 Summary | Full Text:PDF