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IEICE Trans

Keyword : checking sequence

Synthesis of Testable Sequential Circuits with Reduced Checking Sequences
Satoshi SHIBATANI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 739-746
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
sequential circuit, design for testability, automated logic synthesis, checking sequence, state assignment, 
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