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IEICE Trans

Keyword : bit plane coder

Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000
Amit Kumar GUPTA Saeid NOOSHABADI David TAUBMAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/08/01
Vol. E88-D  No. 8 ; pp. 1878-1884
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 2)
Category: Image Processing and Multimedia Systems
Keyword: 
JPEG2000, concurrent symbol processing, bit plane coder, VLSI architecture, 
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