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IEICE Trans

Keyword : array processor

Design Optimization of VLSI Array Processor Architecture for Window Image Processing
Dongju LI Li JIANG Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/08/25
Vol. E82-A  No. 8 ; pp. 1475-1484
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
image processing, array processor, window operation, systolic array, 
 Summary | Full Text:PDF
REMARC: Reconfigurable Multimedia Array Coprocessor
Takashi MIYAMORI Kunle OLUKOTUN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/02/25
Vol. E82-D  No. 2 ; pp. 389-397
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
computer architecture, reconfigurable computer, array processor, multimedia application, 
 Summary | Full Text:PDF
A Hardware Architecture Design Methodology for Hidden Markov Model Based Recognition Systems Using Parallel Processing
Jun-ichi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6 ; pp. 990-1000
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
hidden markov model, speech recognition, corrective training, parallel processing, array processor, system design, 
 Summary | Full Text:PDF