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IEICE Trans

Keyword : Viterbi decoder (VD)

Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders
Ming-Der SHIEH Tai-Ping WANG Chien-Ming WU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/09/01
Vol. E91-D  No. 9 ; pp. 2300-2311
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
Viterbi decoder (VD), in-place scheduling, path metric memory management, VLSI architecture, 
 Summary | Full Text:PDF