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IEICE Trans

Keyword : SD adder

A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation
Shugang WEI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/12/25
Vol. E83-D  No. 12 ; pp. 2056-2064
Type of Manuscript:  PAPER
Category: Theory/Models of Computation
Keyword: 
symmetric residue number system, signed-digit(SD) number representation, SD adder, binary modulo m adder tree, modulo m multiplication, 
 Summary | Full Text:PDF