Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2020/12/01
Vol. E103-D
No. 12 ;
pp. 2494-2503
Type of Manuscript:
Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking)
Category: Computer System
Keyword:
soft processor, FPGA, RISC-V, RV32I, Verilog HDL, five-stage pipelining, |