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Efficient Memory Protection Method for Large-Scale Host-Enclave Data Transfer on Keystone Enclave
Akihiro SAIKI Keiji KIMURA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2026/06/01
Vol. E109-D
No. 6 ;
pp. 894-910
Type of Manuscript:
PAPER
Category: Dependable Computing
Keyword:
TEE, RISC-V, keystone enclave, PMP, memory sharing, | | | Summary | Full Text:PDF | |
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Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
Eiji YOSHIYA Tomoya NAKANISHI Tsuyoshi ISSHIKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2022/07/01
Vol. E105-A
No. 7 ;
pp. 1061-1069
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
IoT, processor, RISC-V, RTL, C++, | | | Summary | Full Text:PDF | |
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