Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs Tsung-Yi WUTzi-Wei KAOHow-Rern LIN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-ANo. 12 ;
pp. 2581-2589 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: clock scheme, globally asynchronous locally synchronous, IR drop, Network-on-Chip,