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IEICE Trans

Keyword : AI chips

6T-8T Hybrid SRAM for Lower-Power Neural-Network Processing by Lowering Operating Voltage
Ji WU Ruoxi YU Kazuteru NAMBA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2024/09/01
Vol. E107-D  No. 9 ; pp. 1278-1280
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
neural network, SRAM, bit error rate (BER), low power consumption, AI chips, 
 Summary | Full Text:PDF