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IEICE Trans

Keyword : wide operating margin

A New Array Architecture for 16 Mb DRAMs with Special Page Mode
Masaki TSUKUDE Tsukasa OISHI Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10 ; pp. 1267-1274
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
array architecture, dynamic memory, high speed access, wide operating margin, low power dissipation, 
 Summary | Full Text:PDF