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IEICE Trans

Keyword : timing margin

A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests
Shunichi KAERIYAMA Mikihiro KAJITA Masayuki MIZUNO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1 ; pp. 102-109
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock generator, duty ratio, frequency synthesis, I/Q balance, jitter, timing margin, 
 Summary | Full Text:PDF