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IEICE Trans

Keyword : sub-sampling PLL

A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC
Sangyeop LEE Kyoya TAKANO Shuhei AMAKAWA Takeshi YOSHIDA Minoru FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2023/10/01
Vol. E106-C  No. 10 ; pp. 533-537
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
sub-sampling PLL, low-supply-voltage, power-scalable, millimeter-wave, CMOS deeply depleted channel (DDC), 
 Summary | Full Text:PDF