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IEICE Trans

Keyword : squashed memory cell

Current-Sensed SRAM Techniques for Megabit-Class Integration--Progress in Operating Frequency by Using Hidden Writing-Recovery Architecture--
Nobutaro SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/11/25
Vol. E82-C  No. 11 ; pp. 2056-2064
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAM, high speed, writing-recovery, current sense, virtual-GND line, squashed memory cell, 
 Summary | Full Text:PDF
Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture
Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1 ; pp. 94-104
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAM, macrocell, size-configurable, high speed, low power, per-bitline architecture, current-sense amplifier, squashed memory cell, trench isolation, 
 Summary | Full Text:PDF