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IEICE Trans

Keyword : single poly gate

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI
Yasue YAMAMOTO Masanori SHIRAHAMA Toshiaki KAWASAKI Ryuji NISHIHARA Shinichi SUMI Yasuhiro AGATA Hirohito KIKUKAWA Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5 ; pp. 1129-1137
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
non-volatile memory, single poly gate, differential cell, CMOS logic process, System-on-Chip (SoC), 
 Summary | Full Text:PDF