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IEICE Trans

Keyword : self timing circuits

Multi-Ported Register File for Reducing the Impact of PVT Variation
Yuuichirou IKEDA Masaya SUMITA Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 356-363
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Signal Integrity and Variability
Keyword: 
multi-ported register file, self timing circuits, PVT variation, crosstalk noise, 
 Summary | Full Text:PDF