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IEICE Trans

Keyword : power-sum

Bit-Parallel Systolic Architecture for AB and AB2 Multiplications over GF(2m)
Kee-Won KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2022/05/01
Vol. E105-C  No. 5 ; pp. 203-206
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
finite fields, modular multiplication, power-sum, systolic array, cryptography, 
 Summary | Full Text:PDF