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IEICE Trans

Keyword : phase-locked-loop

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator
Young-Chan JANG Jun-Hyun BAE Sang-Hune PARK Jae-Yoon SIM Hong-June PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6 ; pp. 1156-1164
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
flash ADC, time-interleaving, phase-locked-loop, digital phase adjuster, digital duty cycle corrector, 
 Summary | Full Text:PDF