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IEICE Trans

Keyword : partial subarray activation

Hierarchical Word-Line Architecture for Large Capacity DRAMs
Tatsunori MUROTANI Tadahiko SUGIBAYASHI Masahide TAKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4 ; pp. 550-556
Type of Manuscript:  INVITED PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: Memory LSI
Keyword: 
DRAM, hierarchical word line, partial subarray activation, 
 Summary | Full Text:PDF