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IEICE Trans

Keyword : non-consecutive basic block buffer

A Microprocessor Architecture Utilizing Histories of Dynamic Sequences Saved in Distributed Memories
Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1398-1407
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
instruction level parallelism, superscalar processors, out-of-order execution, non-consecutive basic block buffer, dynamic speculation of data dependence, 
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