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IEICE Trans

Keyword : multi-threaded execution

Processor Pipeline Design for Fast Network Message Handling in RWC-1 Multiprocessor
Hiroshi MATSUOKA Kazuaki OKAMOTO Hideo HIRONO Mitsuhisa SATO Takashi YOKOTA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1391-1397
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
massively parallel computer, loosely coupled multiprocessor, multi-threaded execution, super-scalar processor, processor pipeline, 
 Summary | Full Text:PDF